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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-30334-1E
MEMORY
CMOS
MASK ROM CARD
PCMCIA Rel.2/JEIDA Ver.4 conformable
MB98A51121/51221/51321/51421/51521-17
MASK ROM CARD 2 M/4 M/8 M/16 M/32 M-BYTE s DESCRIPTION
This card is a PCMCIA and JEIDA-compliant 68-pin two-piece Mask ROM card with the 16-bit mask ROM being installed on the common memory. However, to use this card as PCMCIA Rel.2, JEIDA Ver.4, the card attribute information has to be stored in the Mask ROM.
s FEATURES
* * * * * * * * External dimensions: 85.6 mm x 54.0 mm x 3.3 mm +5 V single power supply Usable in 8 bits x 16 bits configuration Complete static operation I/O level TTL compatible Output tri-state Complete capacitive load without pull-up resistor or pull-down resistor except CE1 and CE2. 68-pin two-piece connector form
s PACKAGE
(CRD-68P-M04)
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MB98A51121/51221/51321/51421/51521-17
s PRODUCT CLASS
Part Number MB98A51121 MB98A51221 MB98A51321 MB98A51421 MB98A51521 Memory Device 16-Mbit Mask ROM x1 pcs 16-Mbit Mask ROM x 2 pcs 16-Mbit Mask ROM x 4 pcs 16-Mbit Mask ROM x 8 pcs 16-Mbit Mask ROM x 16 pcs Memory Configuration (word x bit) 2 M x 8/1 M x 16 4 M x 8/2 M x 16 8 M x 8/4 M x 16 16 M x 8/8 M x 16 32 M x 8/16 M x 16 170 Access Time (ns) (max.)
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MB98A51121/51221/51321/51421/51521-17
s PIN ASSIGNMENTS
Pin No.
(CONNECTOR SIDE)
Symbol GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/N.C. * N.C. VCC N.C. A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND
Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Symbol GND CD1 D11 D12 D13 D14 D15 CE2 VS1 * N.C. N.C. A17 A18 A19 * A20 * A21/N.C. * VCC N.C. A22/N.C. * A23/N.C. * A24/N.C. * A25/N.C. * VS2 * N.C. N.C. N.C. REG/N.C. * BVD2 BVD1 D8 D9 D10 CD2 GND
1 2 3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
35 37 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
(CRD-68P-M02)
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
* Pin Name Symbol A0 to A25 D0 to D15 CE1, CE2 CD1, CD2 * VS1, VS2 REG OE WE BVD1, BVD2 * WP * VCC GND N.C. I/O I I/O I O O I I I O O -- -- -- Pin Name Address input Data I/O Card enable Card detection Voltage sense Attribute memory space select Output enable Write enable Battery voltage detection Write protect Supply voltage (+5 V) Ground No connection
* : Those pins are internally connected; use care when handling.
* : Whether a pin is an address pin or N.C. pin depends on the type of the models. See s DIFFERENCE OF PIN FUNCTIONS.
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MB98A51121/51221/51321/51421/51521-17
s DIFFERENCE OF PIN FUNCTIONS
Part Name MB98A51121 MB98A51221 MB98A51321 MB98A51421 MB98A51521 A21 A22 A23 A24 A21 N.C. A22 N.C. A23 N.C. A24 N.C. A25 N.C. REG N.C. WE N.C. VS1 N.C. VS2 N.C.
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MB98A51121/51221/51321/51421/51521-17
s BLOCK DIAGRAM
1. 16-Mbit Mask ROM x 1/x 2/x 4 Being Mounted
Symbol CE1 CE2 M0 OE REG WE N.C. D0 to D7 D8 to D15 A0 A21 A22 *1 A23 A24 A25 WP A1 to A20 V CC 10 k BVD1 BVD2 VS1 VS2 CD1 CD2 GND A0 to A19 V SS A0 to A19 V SS A0 to A19 V SS A0 to A19 V SS CE CE CE CE I / O buff er O1 to O8 O9 to O16 O1 to O8 O9 to O16 O1 to O8 O9 to O16 O1 to O8 O9 to O16 V CC M1 V CC M2 V CC M3 V CC
100 k
100 k *2: 16-Mbit Mask ROM
OE
OE
OE
OE
*1, *2: Varies with the type of models. Part Number MB98A51121 MB98A51221 MB98A51321 A21 A21 A21 A22 N.C. A22 M0 M0 M0 M0 M1 -- M1 M1 M2 -- -- M2 M3 -- -- M3
N.C. N.C.
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MB98A51121/51221/51321/51421/51521-17
2. 16-Mbit Mask ROM x 8/x 16
*2: 16-Mbit Mask ROM Symbol CE1 CE2 OE A0 CE A22 A23 A24 *1 A25 A1 to A21 I / O buff er CE CE CE CE CE CE CE A0 to A20 A0 to A20 A0 to A20 A0 to A20 A0 to A20 A0 to A20 A0 to A20 A0 to A20 O1 to O8 O1 to O8 O1 to O8 O1 to O8 O1 to O8 O1 to O8 O1 to O8 O1 to O8 REG WE N.C. VS1 VS2 M1 V CC OE OE D0 to D7 D8 to D15 WP V CC 10 k BVD1 BVD2 CD1 CD2 GND I / O buff er CE CE CE CE CE CE CE CE A0 to A20 A0 to A20 A0 to A20 A0 to A20 A0 to A20 A0 to A20 A0 to A20 A0 to A20 O1 to O8 O1 to O8 O1 to O8 O1 to O8 O1 to O8 O1 to O8 O1 to O8 O1 to O8 V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS OE OE OE OE OE OE OE 100 k 100 k M0 V CC M2 V CC M4 V CC M6 V CC M8 V CC M10 V CC M12 V CC M14 V CC
M3 V CC OE
M5 V CC OE
M7 V CC OE
M9 V CC OE
M11 V CC OE
M13 V CC OE
M15 V CC OE
*1, *2: Varies with the type of models. Part Number MB98A51421 MB98A51521 A22 A22 A22 A23 A23 A23 A24 N.C. A24 M0/1 M0/1 M0/1 M2/3 M2/3 M2/3 M4/5 M4/5 M4/5 M6/7 M6/7 M6/7 M8/9 M10/11 M12/13 M14/15 -- -- -- -- M8/9 M10/11 M12/13 M14/15
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MB98A51121/51221/51321/51421/51521-17
s FUNCTIONAL TRUTH TABLE
CE2 H x H H L L CE1 H x L L H L A0 (BYTE) x x L H x x OE x H L L L L Operating Mode Standby Output disable Read (x 8 bit) Read (x 8 bit) Read (x 8 bit) Read (x 16 bit) Output Pin (D8 to D15) High-impedance High-impedance High-impedance High-impedance Output data (odd bytes) Output data (odd bytes) Output Pin (D0 to D7) High-impedance High-impedance Output data (even bytes) Output data (odd bytes) High-impedance Output data (even bytes)
H: High level, L: Low level, x: Don't care
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MB98A51121/51221/51321/51421/51521-17
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Supply Voltage * Input Voltage * Output Voltage * Ambient Temperature Storage Temperature Symbol VCC VIN VOUT TA Tstg Value Max. -0.3 -0.3 -0.3 -10 -30 Min. +6.0 VCC + 0.3 VCC + 0.3 +60 +70 Unit V V V C C
* : The voltage values are with reference to GND = 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage * High Level Input Voltage * Low Level Input Voltage * Ambient Temperature Symbol VCC GND VIH VIL TA Value Min. 4.75 -- 2.4 -0.3 0 Typ. 5.0 0 -- -- -- Max. 5.25 -- VCC + 0.3 0.8 +55 Unit V V V V C
* : The voltage values are with reference to the GND = 0 V. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
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MB98A51121/51221/51321/51421/51521-17
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(On the recommended conditions) Parameter Notes Symbol ISB1 Standby Supply Current ISB2 Averaging Operation Supply Current Input Leak Current Output Leak Current High Level Output Voltage Low Level Output Voltage *1 *2 *2 *2 Test Conditions CE1, CE2 VCC -0.2 V IOUT = 0 mA CE1, CE2 = VIH IOUT = 0 mA Cycle = min. Duty cycle = 100% IOUT = 0 mA, OE = VIH VIN = VIH or VIL VIN = 0 V to VCC VOUT = 0 V to VCC, CE1, CE2 = VIH or OE = VIH IOH = -1 mA IOL = 2.1 mA Value Min. -- -- Typ. 10 -- Max. 1600 10 Unit A mA
ICC ILI ILO VOH VOL
-- -40 -10 2.4 --
-- 0.1 -- -- --
220 40 10 -- 0.4
mA A A V V
Notes: *1. Excluding CE1 and CE2 pins. *2. Excluding WP, BVD1, BVD2, CD1 and CD2 pins.
2. AC Characteristics
(1) Common Memory read cycle (On the recommended conditions) Parameter Read Cycle Time Address Cycle Time Card Enable Access Time Output Enable Access Time Output Disable Time Output Hold Time *1 *2 Notes Symbol tRC tACC tCE tOE tDF tOH CEX = VIH, VIL OE = VIL CEX = VIH, VIL OE = VIL OE = VIL CEX = VIH, VIL -- Test Conditions -- Value Min. 170 -- -- -- -- 0 Max. -- 170 170 75 60 -- Unit ns ns ns ns ns ns
Notes: *1. The maximum delay of OE is tACC - tOE within the ranges in which the tACC is not affected. *2. tDF is determined by either CEX or OE, whichever is faster with rise time. The decision level is determined by the time the output is in a high-impedance state.
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MB98A51121/51221/51321/51421/51521-17
3. Input/output Terminal Capacitance
(VIN, VOUT = GND, f = 1 MHz, TA = +25C) Parameter Input Terminal Capacitance Output Terminal Capacitance Notes *1 *2 Symbol CIN CI/O Value Min. -- -- Max. 75 50 Unit pF pF
Notes: *1. Excluding CE1 and CE2 pins. *2. Excluding WP, BVD1, BVD2, CD1, and CD2 pins.
4. AC Characteristics Test Conditions
Input voltage Input pulse rise time, fall time Timing measurement reference voltage : VIH = 2.6 V, VIL = 0.6 V : tr, tf = 5 ns (0.8 V to 2.4 V) : VIH = 2.4 V : VIL = 0.8 V : VOH = 2.2 V : VOL = 0.8 V : 1TTL + CL (100 pF)
: Input : Output
Output load * Output load circuit
CL
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MB98A51121/51221/51321/51421/51521-17
s TIMING DIAGRAM
1. Common Memory Read Cycle
x 8 bit (CE2 = VIH)
t RC Address VIH VIL t ACC CE1 VIH VIL t CE OE VIH VIL t OE Data Output (D0 to D7) VOH VOL High-impedance state Stabilized output period t OH *: tDF is determined by either OE or CE1, whichever is faster with rise time. The decision level is determined by the time the output is in a high-impedance state. t DF*
x 8 bit (CE1 = VIH)
t RC Address VIH VIL t ACC CE2 VIH VIL t CE OE VIH VIL t OE Data Output (D8 to D15) VOH VOL t OH *: tDF is determined by either OE or CE2, whichever is faster with rise time. The decision level is determined by the time the output is in a high-impedance state. High-impedance state Stabilized output period t DF* A0 is ineffective; do not leave it open, however.
(Continued)
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MB98A51121/51221/51321/51421/51521-17
(Continued)
x 16 bit (CE1 CE2)
t RC Address VIH VIL A 0 is ineffective; do not leave it open, however. t ACC CE1 CE2 VIH VIL t CE OE VIH VIL t OE Data Output (D0 to D15) VOH VOL t OH *: tDF is determined by either OE or CE1 = CE2, whichever is faster with rise time. The decision level is determined by the time the output is in a high-impedance state. High-impedance state Stabilized output period t DF *
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MB98A51121/51221/51321/51421/51521-17
s DATA RELEASE METHOD
Data release is accepted by the 8-Mbit EPROM (1 Mword x 8 bits). To prevent erroneous writing of data, provide three samples per piece of data. Also indicate the card memory address for writing. * Mapping between release data EPROM address and memory card address (16 Mbit Mask ROM x 1/ x 2/ x 4 being mounted)
The range of the address for the MB98A51121 is 000000 to 1FFFFF (2 Mbytes). The range of the address for the MB98A51221 is 000000 to 3FFFFF (4 Mbytes). The range of the address for the MB98A51321 is 000000 to 7FFFFF (8 Mbytes).
3FFFFF
***
Mask ROM No.1 FFFFF
***
Mask ROM No.3 A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0) A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0) 7FFFFF
***
8M EPROM No.3
FFFFF 00002 00001 00000
***
8M EPROM No.7
A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0) A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0)
300002 300001 300000
00002 00001 00000
700002 700001 700000
2FFFFF
***
FFFFF
***
8M EPROM No.2
A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0) A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0)
6FFFFF
***
FFFFF
***
8M EPROM No.7
A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0) A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0)
200002 200001 200000
00002 00001 00000
600002 600001 600000
00002 00001 00000
D7 to D0
D7 to D0
D7 to D0
D7 to D0
1FFFFF
***
Mask ROM No.0 FFFFF
***
Mask ROM No.2 A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0) A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0) 5FFFFF
***
8M EPROM No.1
FFFFF 00002 00001 00000
***
8M EPROM No.5
A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0) A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0)
100002 100001 100000
00002 00001 00000
500002 500001 500000
0FFFFF
***
FFFFF
***
8M EPROM No.0
A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0) A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0)
4FFFFF
***
FFFFF
***
8M EPROM No.4
A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0) A0 = H (Upper bytes D15 to D8) A0 = L (Lower bytes D7 to D0)
000002 000001 000000
00002 00001 00000
400002 400001 400000
00002 00001 00000
D7 to D0
D7 to D0
D7 to D0
D7 to D0
(Continued)
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* Mapping between release data EPROM address and memory card address (16 Mbit Mask ROM x 8/x 16 being mounted)
The range of the address for the MB98A51421 is 000000 to FFFFFF (16 Mbytes). The range of the address for the MB98A51521 is 0000000 to1FFFFFF (32 Mbytes)
03FFFFF
***
Mask ROM No.1 A0 = H (Upper bytes D15 to D8) FFFFF
***
Mask ROM No.3 A0 = H (Upper bytes D15 to D8) FFFFF
***
Mask ROM No.5 A0 = H (Upper bytes D15 to D8) FFFFF
***
Mask ROM No.7 A0 = H (Upper bytes D15 to D8) FFFFF 00002 00001 00000
***
0200005 0200003 0200001
00002 00001 00000
07FFFFF 8M EPROM 0600005 0600003 No.3 0600001
***
00002 00001 00000
0BFFFFF 8M EPROM 0A00005 0A00003 No.7 0A00001
***
00002 00001 00000
0FFFFFF 8M EPROM 0E00005 0E00003 No.11 0E00001
***
8M EPROM No.15
01FFFFF
***
FFFFF
***
0000005 0000003 0000001
00002 00001 00000
05FFFFF 8M EPROM 0400005 0400003 No.2 0400001
***
FFFFF
***
00002 00001 00000
09FFFFF 8M EPROM 0800005 0800003 No.6 0800001
***
FFFFF
***
00002 00001 00000
0DFFFFF 8M EPROM 0C00005 No.10 0C00003 0C00001
***
FFFFF 00002 00001 00000
***
8M EPROM No.14
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
03FFFFE
***
Mask ROM No.0 A0 = L (Lower bytes D7 to D0) FFFFF
***
Mask ROM No.2 A0 = L (Lower bytes D7 to D0) FFFFF
***
Mask ROM No.4 A0 = L (Lower bytes D7 to D0) FFFFF
***
Mask ROM No.6 A0 = L (Lower bytes D7 to D0) FFFFF 00002 00001 00000
***
0200004 0200002 0200000
00002 00001 00000
07FFFFE 8M EPROM 0600004 0600002 No.1 0600000
***
00002 00001 00000
0BFFFFE 8M EPROM 0A00004 0A00002 No.5 0A00000
***
00002 00001 00000
0FFFFFE 8M EPROM 0E00004 0E00002 No.9 0E00000
***
8M EPROM No.13
01FFFFE
***
FFFFF
***
0000004 0000002 0000000
00002 00001 00000
05FFFFE 8M EPROM 0400004 0400002 No.0 0400000
***
FFFFF
***
00002 00001 00000
09FFFFE 8M EPROM 0800004 0800002 No.4 0800000
***
FFFFF
***
00002 00001 00000
0DFFFFE 8M EPROM 0C00004 0C00002 No.8 0C00000
***
FFFFF 00002 00001 00000
***
8M EPROM No.12
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
(Continued)
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MB98A51121/51221/51321/51421/51521-17
(Continued)
13FFFFF
***
Mask ROM No.9 A0 = H (Upper bytes D15 to D8) FFFFF
***
Mask ROM No.11 A0 = H (Upper bytes D15 to D8) FFFFF
***
Mask ROM No.13 A0 = H (Upper bytes D15 to D8) FFFFF
***
Mask ROM No.15 A0 = H (Upper bytes D15 to D8) FFFFF 00002 00001 00000
***
1200005 1200003 1200001
00002 00001 00000
17FFFFF 8M EPROM 1600005 1600003 No.19 1600001
***
00002 00001 00000
1BFFFFF 8M EPROM 1A00005 No.23 1A00003 1A00001
***
00002 00001 00000
1FFFFFF 8M EPROM 1E00005 No.27 1E00003 1E00001
***
8M EPROM No.31
11FFFFF
***
FFFFF
***
1000005 1000003 1000001
00002 00001 00000
15FFFFF 8M EPROM 1400005 No.18 1400003 1400001
***
FFFFF
***
00002 00001 00000
19FFFFF 8M EPROM 1800005 No.22 1800003 1800001
***
FFFFF 00002 00001 00000
***
1DFFFFF 8M EPROM 1C00005 No.26 1C00003 1C00001
***
FFFFF 00002 00001 00000
***
8M EPROM No.30
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
13FFFFE
***
Mask ROM No.8 A0 = L (Lower bytes D7 to D0) FFFFF
***
Mask ROM No.10 A0 = L (Lower bytes D7 to D0) FFFFF
***
Mask ROM No.12 A0 = L (Lower bytes D7 to D0) FFFFF
***
Mask ROM No.14 A0 = L (Lower bytes D7 to D0) FFFFF 00002 00001 00000
***
1200004 1200002 1200000
00002 00001 00000
17FFFFE 8M EPROM 1600004 1600002 No.17 1600000
***
00002 00001 00000
1BFFFFE 8M EPROM 1A00004 No.21 1A00002 1A00000
***
00002 00001 00000
1FFFFFE 8M EPROM 1E00004 No.25 1E00002 1E00000
***
8M EPROM No.29
11FFFFE
***
FFFFF
***
1000004 1000002 1000000
00002 00001 00000
15FFFFE 8M EPROM 1400004 No.16 1400002 1400000
***
FFFFF 00002 00001 00000
***
19FFFFE 8M EPROM 1800004 No.20 1800002 1800000
***
FFFFF
***
00002 00001 00000
1DFFFFE 8M EPROM 1C00004 No.24 1C00002 1C00000
***
FFFFF 00002 00001 00000
***
8M EPROM No.28
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
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MB98A51121/51221/51321/51421/51521-17
s AUXILIARY CAPABILITIES
1. Card Detection Pins (CD1, CD2)
These pins verify a card is correctly inserted into the system. The two pins are internally connected to the ground; with the system side connection being pulled up to the VCC, detection of the voltage of these pins allows the system to check the state of connectivity of a card (See the diagram below).
V cc A V cc B CD2 CD1
System side
Card side
2. Write Protection Pin (WP)
The Mask ROM Card, whose common memory is write-protected, outputs a high-level write-protection signal.
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MB98A51121/51221/51321/51421/51521-17
s DEVICE HANDLING PRECAUTIONS
The device in composed of fine electronic parts, so take care in handling or keeping it as below. * The card is made fine, so do not keep it in the high temperature nor high humiditly, place line in the direct sunshine nor near the heater. * The card should not be bent, scratched, dropped nor be shocked violently. * This device should never be taken a part. It could destroy the card or your personal computer hardware. * To help you handle this device safely, request us the device specifications when purchasing this device.
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MB98A51121/51221/51321/51421/51521-17
s PACKAGE DIMENSIONS
68-pin Memory Card (CRD-68P-M02)
Note: Dimensions conform with PCMCIA/JEIDA
1.600.05 (.063.002)
2-R0.50(.020)
85.600.20(3.370.008) 10.50(.413)
2-R2.00(.079)
1.000.05 (.039.002) 41.91 (1.650) REF 1.000.05 (.039.002) "A" "C" 1.000.05 (.039.002) 10.50(.413) 54.000.10 (2.126.004)
3.300.10(.130.004)
"B" CONNECTOR PORTION
3.300.20(.130.008) CARD BODY
Details of "A" part Details of "B" part 1.270.10(.050.004)TYP 1PIN 1.270.10 (.050.004) 1.00(.039) 6.00(.236) Details of "C" part
C
1994 FUJITSU LIMITED K68002SC-5-1
Dimensions in mm (inches)
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MB98A51121/51221/51321/51421/51521-17
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9704 (c) FUJITSU LIMITED Printed in Japan
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